Digital two-speed motor control

ABSTRACT

A remote digital two-speed motor control, for controlling frequency or bandwidth tuning of a jamming transmitter. A digitally controlled transistor switches the speed of a motor after a predetermined time delay. The motor may be retained in the initial speed by continuous resetting of the digital circuit before the timing circuit reaches a firing voltage.

United States atent 1 Sailer 1 Aug. M, 1973 DIGITAL TWO-SPEED MOTORCONTROL 5 Primary Examiner-Bernard A. Gilheany l V if. 1 mentor Henrysauer emura Ca 1 Assistant Examiner-Thomas Langer [73] Assignee: TheUnited States of America as v Attorney- Richard S. Sciascia, .l. M.Amand and represented by the Secretary of the D id OReiIIy Navy,Washington, DC.

[22] Filed: May 8, 1972 [57] [2]] Appl. No.: 251,063

A remote digital two-speed motor control, for controlling frequency orbandwidth tuning of a jamming trans- [52] US. Cl. 3118/305, 318/345mitten A digitally controlled transistor switches the 1 Int. Cl. speedofa motor after a predetermined time delay. The

[58] Field of Search 318/276, 305, 345, motor may be retained in theinitial speed by cominw 318591 318 ous resetting of the digital circuitbefore the timing circuit reaches a firing voltage.

[56] References Cited UNITED STATES PATENTS 10 C, 2 Drawing Figures3,546,530 12/1970 Simonsen 318/326 PATENTED M38 14 3973 SHEEI 1 0F 2JOIPZOU 3:05

1 DIGITAL TWO-SPEED MOTOR CONTROL BACKGROUND OF THE INVENTION Thepresent invention relates generally to digital switching circuits andmore particularly relates to digital control of a motor.

In many applications, particularly in aircraft, the number of switchingand control functions are so great that wire bundle size is verycritical. Therefore, any improvements which reduce the number of controlwires provide a distinct advantage. Presently, ECM (electroniccountermeasure) systems that have jamming frequency and/or jammingbandwidth tuning require a minimum of one potentiometer and threecontrol wires. The potentiometer is located in the aircraft cockpit andthe three wires extend from the cockpit to external stores. Thepotentiometer controls a motor which in turn tunes the frequency and/orbandwidth of a jamming transmitter through a series of clutches. Thepresent invention performs the same functions but utilizes only onecontrol wire.

SUMMARY OF THE INVENTION The purpose of the present invention is toprovide a two-speed motor control with a minimum of control wires. Thisis accomplished by digital control of a transistor which switches thespeed of a motor after a predetermined time. A timing circuitautomatically changes the speed of a motor by changing the state of aset-reset flip-flop after a predetermined time delay. The motor can beretained in the initial speed by continuous resetting of the flip-flopbefore the timing circuit builds up to a firing voltage. The motorcontrols the frequency and bandwidth tuning of a jamming transmitter.

One object of the present invention is to provide a two-speed motorcontrol having a minimum of control wires.

Another object of the invention is to provide a remote digital two-speedmotor control for controlling the ECM functions of jammer frequencytuning and jammer bandwidth tuning.

Other objects, advantages and novel features of the invention willbecome apparent from the following detailed description of the inventionwhen considered in conjunction with the accompanying drawings wherein:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of thedigital two-speed motor control.

FIG. 2 is a schematic of the digital two-speed motor adapted to tune thefrequency and bandwidth of a jamming transmitter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows in schematic formthe novel digital twospeed motor control circuit. The circuit iscomprised of inhibit control 10, pulse timing control 12, invertingpulse amplifier 14, reset-set flip-flop 16, power amplifier gate 18,output control 20, and d.c. motor 22. Inhibit control is provided bysilicon controlled rectifier Q1 while pulse timing control 12 iscomprised of a unijunction transistor 02 receiving an input from a timeconstant circuit. Reset-set flip-flop action is provided by anintegrated circuit having quadruple twoinput NAND gates. Power amplifier18 is also an inte grated circuit having dual NAND power gates. Bothintegrated circuits have a steady state input of +5 volts. They areoperated by applying a low input of 0 volts (ground) to the gates.

In the preferred embodiment, the d.c. motor 22 provides fine and coarsetuning of frequency and bandwidth in a jamming transmitter through aseries of clutches. It will be readily apparent, however, that the novelcircuit has other applications.

Power is initially applied to d.c. motor 22 through resistor R1 l whichis selected to provide the desired slow speed for fine tuning of ajamming transmitter or other device. Output control transistor Q4 shuntsslow speed control resistor R11 and switches the motor to fast speed forcoarse tuning when it is turned on. This occurs automatically after apredetermined time set in the pulse timing control 12.

Fast speed is automatically controlled by pulse timing control 12,inverting pulse amplifier 14, reset-set flipflop l6 and power amplifier18 which operate to turn output control transistor Q4 on. In the pulsetiming control 12, unijunction transistor Q2 produces a pulse whencapacitor C1 reaches firing voltage according to the time constant ofR2, R3 and C1, In the preferred embodiment the time constant can bevaried between approximately 0.25 and 1 sec by adjusting R3.

The pulse output from pulse timing control 12 is amplified and invertedby transistor Q3 of the inverting pulse amplifier. The pulse is appliedto the reset-set flip-flop and produces a high output to gate G1 ofpower amplifier 16. Output control transistor Q4 is then turned onbypassing resistor R11, changing d.c. motor to fast speed.

At this time, Q1 of inhibit control 10 is off which permits C1 tobuild-up to firing voltage according to the time constant of R2, R3 andC1. A high (i.e., an open circuit) digital input applied at A resetsflip-flop 16 and produces a high output from gate G6 of power amplifier18. This output turns transistor Q1 on, inhibiting C1 from reachingfiring voltage.

The high (open circuit) digital input at A is also applied to relay coilKl through another digital circuit (now shown) and opens the contacts ofthe relay. When point A is again switched to a low digital input (0V), alow is applied through a digital circuit (not shown) to relay coil K1,closing its contacts and d.c. motor 22 begins operating at slow speed.The low at point A produces a low on the gate of Q1 turning it off andcapacitor C1 begins to charge up to a firing voltage according to thetime constant of R2, R3 and C1.

Because of the cross-coupling of the outputs of gates G1 and G2 offlip-flop 16, it will act as a RS (reset-set) memory. That is, only atransition from a high to a low on the inputs of gates G1 or G2 willchange the output. A low input at point A will turn Q1 of inhibitcontrol 10 off, permitting capacitor C1 to charge to firing voltage.When Cl fires it will supply a low to the input of gate G1 of flip-flop16, changing the motor 22 to high speed. It will remain in high speeduntil there is a transition from a high to a low (i.e., a high input atpoint A) on the input of gate G2. Capacitor C1 is permitted to continuefiring just in case a transient should change the input on gate G2 to alow.

To retain d.c. motor 22 in slow speed, the operator must jog point A(i.e., switch from a low to a high and back to a low) before timeconstanttcircuit R2, R3 and C1 reaches a firing voltage. If a high (opencircuit) digital input is left on point A, the contacts of relay K1 willopen and d.c. motor 22 will stop. The motor 22 will not start againuntil a low (ground) is applied at point A.

As an alternative, the time constant of timing control circuit can be afixed value. Once an optimum setting for R3 is determined, resistors R2and R3 can be replaced with a fixed resistor.

With the present design, the circuit provides stop, slow speed controland automatic fast speed after a predetermined time delay. If desired, aslight modification of the circuit will provide the reverse functions.That is, stop, fast speed control and automatic slow-speed after apredetermined time delay. This can be done by substituting an NPNtransistor for the PNP transistor O4 in output control 20.

With a low (ground) digital input applied at point A, the contacts ofrelay K1 are closed and power is now applied to d.c. motor 22 throughNPN transistor Q4. Thus, the motor 22 is operating at high speed. Thelow input at point A produces a low on Q1 which turns it off and Clstarts charging to firing voltage. Cl firesaccording to the timeconstant of R2, R3 as before except that Q4, which is now an NPNtransistor is turned off. This switches the motor to slow speed becausepower is now being supplied to the motor through-resistor R11.

FIG. 2 is a schematic diagram of a particular circuit utilizing thenovel circuit to control both frequency and bandwidth tuning of ajamming transmitter. The operator must be able to tune across thefrequency spectrum in either direction. Thus, this circuit incorporatesseparate inputs for frequency and bandwidth and a relay which reversesthe motor 22.

Switches S1 and 82 provide selection of frequency or bandwidth in eitherthe forward or reverse direction. The switches shown are two-sectiontoggle switches but other switches or circuit configurations may beused. The important thing is that only a single wire is needed forbandwidth or frequency control rather than three for each with thepresent potentiometer method of control.

Frequency or bandwidth and forward or reverse motor control is providedthrough a plurality of NAND gates 24 and power gates 26 which operaterelays K1 to K4. Relay K1 operates motor in the forward direction whilerelay K2 in conjunction with relay K controls reverse operation. Motor22 is connected to slip clutch 28 and operates frequency magnetic clutch30 or bandwidth magnetic clutch 32. Each magnetic clutch is mechanicallyconnected to a potentiometer (not shown) for frequency or bandwidthadjustment. Additional control functions can be added by using analternate integrated circuit with a gate expander for Q1 siliconcontrolled rectifier Q2 unijunction transistor Q3 transistor Q4 PNP orNPN transistor As indicated earlier, the value selected for R3 gives atime constant between 0.25 and I second but could be fixed at someoptimum value for a particular application. Integrated circuits for theflip-flop and power amplifier were provided by Texas Instrument part no.Tl 15846N and Motorola Corp. part no. MC844P, respectively. The valuefor R11 is selected to provide any desired slow speed of the motor.

Thus, there has been disclosed a digital two-speed motor control havinga minimum of control wires and particularly suitable for aircraft use intuning frequency or bandwidth of a jamming transmitter.

Obviously, many modifications and variations of the present inventionare possible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed is:

l. A digital two-speed motor control comprising:

a motor;

a power source connected to said motor; resistive means connectedbetween said power source and said motor for operating the motor at apredetermined slow speed;

a transistor control connected in parallel with said resistive means forchanging the motor to fast a speed;

means for switching said transistor control on; said switching meanscomprising a flip-flop adapted to switch said transistor control on whenit produces a high output; a power gate for amplifying the output of theflip-flop and applying it to the transistor control;

means for changing the output of the flip-flop to a low state and backto a high state after a predetermined time; said means comprising aswitch for changing the input of the flip-flop to a high state; timingmeans for producing a pulse after a predetennined time constant expires;pulse inverting means connected to said timing means for applying saidpulse to said flip-flop; and inhibiting means for preventing the timingmeans from reaching firing voltage; said inhibiting means connected tothe flip-flop through the power gate and adapted to be energized by saidflip-flop when it receives a high input.

2. The control system of claim 1 wherein said transistor is a PNPtransistor whereby said motor is initially in slow speed and switches tohigh speed after a predetermined time.

3. The control system of claim 1 wherein said transistor is an NPNtransistor whereby said motor is initially in fast speed and switches toslow speed after a predetermined time.

4. The control system of claim 1 wherein said timing means has anadjustable resistive-capacitive time constant.

5. The control system of claim 4 wherein said inhibit- 5 ing means is asilicon controlled rectifier with its gate 3 ,75 3 ,066 5 6 7. Thecontrol system of claim 6 wherein said tuning 10. The control system ofclaim 9 wherein said means means comprises a series of clutchesconnected to said f Selecting frequency or b d d tuning and motor. r

atm said motor in the forward or reverse direction 8. The control systemof claim 7 including means for 3 Selecting frequency or bandwidth tuning5 comprises a plurality of NAND gates; power gates and 9. The controlsystem of claim 8 including means for relays connected to the input ofsaid ppoperating said motor in forward or reverse direction.

1. A digital two-speed motor control comprising: a motor; a power sourceconnected to said motor; resistive means connected between said powersource and said motor for opeRating the motor at a predetermined slowspeed; a transistor control connected in parallel with said resistivemeans for changing the motor to fast speed; means for switching saidtransistor control on; said switching means comprising a flip-flopadapted to switch said transistor control on when it produces a highoutput; a power gate for amplifying the output of the flip-flop andapplying it to the transistor control; means for changing the output ofthe flip-flop to a low state and back to a high state after apredetermined time; said means comprising a switch for changing theinput of the flip-flop to a high state; timing means for producing apulse after a predetermined time constant expires; pulse inverting meansconnected to said timing means for applying said pulse to saidflip-flop; and inhibiting means for preventing the timing means fromreaching firing voltage; said inhibiting means connected to theflip-flop through the power gate and adapted to be energized by saidflip-flop when it receives a high input.
 2. The control system of claim1 wherein said transistor is a PNP transistor whereby said motor isinitially in slow speed and switches to high speed after a predeterminedtime.
 3. The control system of claim 1 wherein said transistor is an NPNtransistor whereby said motor is initially in fast speed and switches toslow speed after a predetermined time.
 4. The control system of claim 1wherein said timing means has an adjustable resistive-capacitive timeconstant.
 5. The control system of claim 4 wherein said inhibiting meansis a silicon controlled rectifier with its gate connected to theflip-flop through the power gate.
 6. The control system of claim 5including means for tuning a jamming transmitter.
 7. The control systemof claim 6 wherein said tuning means comprises a series of clutchesconnected to said motor.
 8. The control system of claim 7 includingmeans for selecting frequency or bandwidth tuning.
 9. The control systemof claim 8 including means for operating said motor in forward orreverse direction.
 10. The control system of claim 9 wherein said meansfor selecting frequency or bandwidth tuning and operating said motor inthe forward or reverse direction comprises a plurality of NAND gates;power gates and relays connected to the input of said flip-flop.